1. Field of the Invention
The present invention relates to a communication Interface between a single system serving as a master (hereinafter, referred to as a xe2x80x9cmaster systemxe2x80x9d) and a plurality of systems serving as slaves (hereinafter, referred to as xe2x80x9cslave systemsxe2x80x9d).
2. Description of the Related Art
Various communication interfaces have been proposed and standardized in the art for communicating a plurality of systems with one another. Examples of such conventional communication interfaces used between a master system and one or more slave systems will now be described.
As a first conventional example, a conventional PC card ATA I/O mode interface will be described below.
FIG. 13 illustrates signal lines included in a conventional PC card ATA I/O mode interface. Referring to FIG. 13, the conventional PC card ATA I/O mode interface includes: signal lines 101 (xe2x80x9cA00xe2x80x9d-xe2x80x9cA10xe2x80x9d) through which an address is input by designating one of addresses A00-A10 in a slave system to be accessed by a master system; data input/output signal lines 102 (xe2x80x9cD00xe2x80x9d-xe2x80x9cD15xe2x80x9d) for data/command/status information; a signal line 103 (xe2x80x9c-CExe2x80x9d) through which the master system selects one of a plurality of slave systems: a signal line 105 (xe2x80x9c-IREQxe2x80x9d) through which the master system is notified of the internal operation state of the slave system: a write control signal line 106 (xe2x80x9c-IOWRxe2x80x9d) through which the master system controls outputs from the master system to the signal lines 102 and inputs to the slave system; and a read control signal line 107 (xe2x80x9c-IORDxe2x80x9d) through which the master system controls outputs from the slave system to the signal lines 102 and inputs to the master system.
A basic operation, i.e., a read/write operation, of a conventional communication system including these signal lines connected between the master system and the slave systems will now be described.
Each of FIGS. 14A and 14B is a timing diagram illustrating a communication protocol for use in the conventional PC card ATA I/O mode interface.
FIG. 14A illustrates a conventional method by which the signal lines are operated when the master system reads data from a slave system. The master system controls the slave system selection signal line 103 to go low so as to select one of the slave systems with which the master system is to communicate. Then, the master system transmits a register address in the slave system at which a read address is to be stored and the read address to the address signal lines 101 and the data input/output signal lines 102, respectively. At the same time, the master system controls the write control signal line 106, through which inputs to the slave system are controlled, to go low. The write control signal line 106 is kept low for a predetermined period and is then controlled to go high, thereby setting the address register in the slave system, which indicates the address from which data is to be read out. The address of the data to be read out is designated by repeating this operation of setting the address register in the slave system using the address signal lines 101, the data input/output signal lines 102 and the write control signal line 106. Then, the register address in the slave system for storing the command address and prescribed data, which indicates a read command, is transmitted to the address signal lines 101 and the data input/output signal lines 102, respectively, in order to issue a read command to the slave system. At the same time, the write control signal line 106, through which inputs to the slave system are controlled, is kept low for a predetermined period and is then controlled to go high, whereby the slave system interprets the data received from the data input/output signal lines 102 in order to determine whether a read request has been issued from the master system, thereby starting to read data from a memory device in the slave system. Thereafter, when the read data is ready, the slave system controls the signal line 105, which indicates the internal state of the slave system, to go low. The master system detects the high-to-low transition of the signal line 105, which indicates the internal state of the slave system, after which the master system transmits the address of the status register of the slave system to the address signal lines 101. At the same time, the master system controls the read control signal line 107, through which outputs from the slave system are controlled, to go low. The master system keeps the read control signal line 107 low for a predetermined period and then controls the read control signal line 107 to go high, thereby receiving the status of the slave system through the data input/output signal lines 102. Thereafter, the master system transmits the address of the data register of the slave system to the address signal lines 101. At the same time, the master system controls the read control signal line 107, through which outputs from the slave system are controlled, to go low. The master system keeps the read control signal line 107 low for a predetermined period and then controls the read control signal line 107 to go high. Thus, the operation of receiving the read data through the data input/output signal lines 102 is repeated so that the master system receives data having a particular data length from the slave system.
FIG. 14B illustrates a conventional method by which the signal lines are operated when the master system writes data to a slave system. Setting of an address register which indicates the address at which data is to be written is performed by a manner similar to that illustrated in FIG. 14A. Then, the register address in the slave system for storing the command address and prescribed data which Indicates a write command is transmitted to the address signal lines 101 and the data input/output signal lines 102 respectively, in order to issue a write command to the slave system. At the same time, the write control signal line 106, through which inputs to the slave system are controlled, is kept low for a predetermined period and is then controlled to go high, whereby the slave system interprets the data received from the data input/output signal lines 102 in order to determine whether a write request has been issued from the master system, and the slave system waits for write data. Then, the master system transmits the address of the data register of the slave system to the address signal lines 101. At the same time, the write control signal line 106, through which inputs to the slave system are controlled, is kept low for a predetermined period and is then controlled to go high. Thus, the operation of transmitting the write data through the data input/output signal lines 102 is repeated so that the master system transmits data having a particular data length to the slave system. When the transmission is complete, the slave system writes write data in a memory device in the slave system. When the write operation is complete, the signal line 105, which indicates the internal state of the slave system, is controlled to go low. The master system detects the high-to-low transition of the signal line 105, which indicates the internal state of the slave system, after which the master system transmits the address of the status register of the slate system to the address signal lines 101. At the same time the master system controls the read control signal line 107, through which output from the slave system are controlled to go low. The master system keeps the read control signal line 107 low for a predetermined period and then controls the read control signal line 107 to go high, thereby receiving the status of the slave system through the date input/output signal lines 102 in order to confirm completion of the operation.
As a second conventional example, a conventional microcontroller interface will be described below.
FIG. 15 illustrates signal lines Included in a conventional microcontroller interface. Referring to FIG. 15 the conventional microcontroller interface includes a slave system selection signal line 111 (xe2x80x9c-CSxe2x80x9d), a clock signal line 112 (xe2x80x9cCLKxe2x80x9d) for synchronization of communicated data; a data input signal line 113 (xe2x80x9cData Inxe2x80x9d) through which data is input from the master system to the slave system; and a data output signal line 114 (xe2x80x9cData Outxe2x80x9d) through which data is output from the slave system to the master system.
An operation of a communication system including these signal lines connected between the master system and the slave systems will now be described.
Each of FIGS. 16A and 16B is a timing diagram illustrating a communication protocol for use in the conventional microcontroller.
FIG. 16A is a timing diagram illustrating a conventional method by which the signal lines are operated when the master system of the conventional microcontroller reads data from a slave system. The master system controls the slave system selection signal line 111 to go low so as to select one of the slave systems with which the master system is to communicate. The master system transmits a read command having a predetermined data length to the data input signal line 113 in synchronism with the clock signal on the clock signal line 112. The data input signal line 113 is initially kept high. A high-to-low transition of the data input signal line 113 triggers the slave system to start receiving the command therefrom. During this operation, the slave system keeps the data output signal line 114 high, and interprets the command received from the master system, after which the slave system transmits command reception response data to the data output signal line 114 in synchronism with the clock signal on the clock signal line 112. First, the slave system controls the data output signal line 114 to go low, and then transmits response data having a predetermined data length, after which the slave system again keeps the data output signal line 114 high. On the other hand, the master system is triggered by a high-to-low transition of the data output signal line 114 to start receiving the data from the slave system. The master system receives as command reception response data the subsequent output data which has a predetermined data length. The master system continues to transmit a clock signal to the clock signal line 112 even after confirming a normal operation by receiving command reception response data from the slave system, thereby preparing to receive data transmitted by the slave system through the data output signal line 114. The master system is triggered by a high-to-low transition of the data output signal line 114 to receive the subsequent data as read data from the data output signal line 114 which has a predetermined data length.
FIG. 16B is a timing diagram illustrating a conventional method by which the signal lines are operated when the master system of the conventional microcontroller writes data to a slave system. The master system controls the slave system selection signal line 111 to go low so as to select one of the slave systems with which the master system is to communicate. The master system transmits a write command having a predetermined data length to the data input signal line 113 in synchronism with the clock signal on the clock signal line 112. The data input signal line 113 is initially kept high. A high-to-low transition of the data input signal line 113 triggers the slave system to start receiving data therefrom. During this operation, the slave system keeps the data output signal line 114 high, and interprets the command received from the master system, after which the slave system transmits command reception response data to the data output signal line 114 in synchronism with the clock signal an the clock signal line 112. First, the slave system controls the data output signal line 114 to go low, and then transmits response data having a predetermined data length, after which the slave system again keeps the data output signal line 114 high. On the other hand, the master system is triggered by a high-to-low transition of the data output signal line 114 to start receiving the data from the slave system. The master system receives as command reception response data the subsequent output data which has a predetermined data length. After confirming a normal operation by receiving command reception response data, the master system controls the data input signal line 113 to go low in synchronism with the clock signal on the data clock line 112 and transmits write data having a predetermined data length to the data input signal line 113. Finally, the master system controls the data input signal line 113 to go high. The slave system is triggered by a high-to-low transition of the data input signal line 113 to receive the write data and write the received data in a memory device. The slave system controls the data output signal line 114 to go low and transmits a write operation completion response through the data output signal line 114. The master system is triggered by a high-to-low transition of the signal received through the data output signal line 114 to receive the subsequent data as response data from the data output signal line 114 which has a predetermined data length, thereby confirming the write operation.
The communication interface of the first conventional example, which is defined as the ANSI ATA standard, is commonly used in communication between a personal computer and a PC card. As described above, the communication interface is characterized by the use of many signal lines such as the address/data/control signal lines, and has a specification which is designed to maintain a communication compatibility with existing personal computers. However, because of the use of many signal lines for communication, the communication interface is not suitable for a system in which a reduction in physical size is demanded.
The communication interface of the second conventional example, as described above, has only four signal lines, and is therefore suitable as a communication interface for use with small apparatuses. However in order to increase the data transfer rate, It is necessary to increase the number of data lines. In this conventional communication interface, Independent signal lines are used for input and output of data signals. For example, when such a system is designed with 4-bit data lines, a total of 8 data lines will be required, thereby significantly increasing the number of signal lines and making the communication interface less suitable for small systems.
According to one aspect of this invention, a communication interface includes a clock signal line, a first signal line, a second signal line and one or more data signal lines as communication signal lines between a master system and a slave system.
In one embodiment of the invention, the first signal line is used both for transmitting a signal from the master system to the slave system and for transmitting a signal from the slave system to the master system.
In one embodiment of the invention, the master system transmits a signal to the clock signal line only when the first signal line is activated by the master system or the slave system, and the master system stops transmitting the clock signal to the clock signal line when the first signal line is not activated.
In one embodiment of the invention, the second signal line is used both for transmitting an initialization signal from the master system to the slave system and for transmitting a detection signal from the slave system to the master system.
In one embodiment of the invention, the first signal line is connected to a first predetermined potential via a first resistor element, and the second signal line is connected a second predetermined potential via a second resistor element.
In one embodiment of the invention, the master system transmits a cloak signal to the clock signal line after the slave system has activated the first signal line. The master system stops transmitting the signal to the clock signal line after the slave system stops activation of the first signal line. After a predetermined period of time has passed after the master system has stopped transmitting the clock signal to the clock signal line, the master system activates the first signal line and transmits the clock signal to the clock signal line. The master system and the slave system communicate with each other via the data signal line in synchronism with the clock signal on the clock signal line. After the communication is completed, the master system stops activation of the first signal line while simultaneously stopping transmission of the clock signal to the clock signal line.
Based on the above-described configuration, it is possible to communicate the master system and the slave systems with each other with a minimum number of signal lines.
Thus, the invention described herein makes possible the advantage of providing a small communication interface used between a single master system and a plurality of slave systems, which is capable of communicating the master system and the slave systems with each other with a minimum number of signal lines.